module consumer (clock, v_i, r_o, d_i);
	input clock;
	input  v_i;
	output r_o;
	input [15:0] d_i;
	wire x_low_bit;
	reg [31:0] x_rand;


	initial  begin
		x_rand <= x_rand ^ 32'h55555555;
	end
	
	always @(posedge clock) begin
		 x_rand <= {x_rand[30:0], r_o} ;
	end 
	
	assign r_o = x_rand[27] ^ x_rand[15];
	

endmodule 